25 #ifndef _GLIBCXX_EXPERIMENTAL_SIMD_DETAIL_H_
26 #define _GLIBCXX_EXPERIMENTAL_SIMD_DETAIL_H_
28 #if __cplusplus >= 201703L
34 #define _GLIBCXX_SIMD_BEGIN_NAMESPACE \
35 namespace std _GLIBCXX_VISIBILITY(default) \
37 _GLIBCXX_BEGIN_NAMESPACE_VERSION \
38 namespace experimental { \
39 inline namespace parallelism_v2 {
40 #define _GLIBCXX_SIMD_END_NAMESPACE \
43 _GLIBCXX_END_NAMESPACE_VERSION \
48 #if defined __ARM_NEON
49 #define _GLIBCXX_SIMD_HAVE_NEON 1
51 #define _GLIBCXX_SIMD_HAVE_NEON 0
53 #if defined __ARM_NEON && (__ARM_ARCH >= 8 || defined __aarch64__)
54 #define _GLIBCXX_SIMD_HAVE_NEON_A32 1
56 #define _GLIBCXX_SIMD_HAVE_NEON_A32 0
58 #if defined __ARM_NEON && defined __aarch64__
59 #define _GLIBCXX_SIMD_HAVE_NEON_A64 1
61 #define _GLIBCXX_SIMD_HAVE_NEON_A64 0
66 #define _GLIBCXX_SIMD_HAVE_MMX 1
68 #define _GLIBCXX_SIMD_HAVE_MMX 0
70 #if defined __SSE__ || defined __x86_64__
71 #define _GLIBCXX_SIMD_HAVE_SSE 1
73 #define _GLIBCXX_SIMD_HAVE_SSE 0
75 #if defined __SSE2__ || defined __x86_64__
76 #define _GLIBCXX_SIMD_HAVE_SSE2 1
78 #define _GLIBCXX_SIMD_HAVE_SSE2 0
81 #define _GLIBCXX_SIMD_HAVE_SSE3 1
83 #define _GLIBCXX_SIMD_HAVE_SSE3 0
86 #define _GLIBCXX_SIMD_HAVE_SSSE3 1
88 #define _GLIBCXX_SIMD_HAVE_SSSE3 0
91 #define _GLIBCXX_SIMD_HAVE_SSE4_1 1
93 #define _GLIBCXX_SIMD_HAVE_SSE4_1 0
96 #define _GLIBCXX_SIMD_HAVE_SSE4_2 1
98 #define _GLIBCXX_SIMD_HAVE_SSE4_2 0
101 #define _GLIBCXX_SIMD_HAVE_XOP 1
103 #define _GLIBCXX_SIMD_HAVE_XOP 0
106 #define _GLIBCXX_SIMD_HAVE_AVX 1
108 #define _GLIBCXX_SIMD_HAVE_AVX 0
111 #define _GLIBCXX_SIMD_HAVE_AVX2 1
113 #define _GLIBCXX_SIMD_HAVE_AVX2 0
116 #define _GLIBCXX_SIMD_HAVE_BMI1 1
118 #define _GLIBCXX_SIMD_HAVE_BMI1 0
121 #define _GLIBCXX_SIMD_HAVE_BMI2 1
123 #define _GLIBCXX_SIMD_HAVE_BMI2 0
126 #define _GLIBCXX_SIMD_HAVE_LZCNT 1
128 #define _GLIBCXX_SIMD_HAVE_LZCNT 0
131 #define _GLIBCXX_SIMD_HAVE_SSE4A 1
133 #define _GLIBCXX_SIMD_HAVE_SSE4A 0
136 #define _GLIBCXX_SIMD_HAVE_FMA 1
138 #define _GLIBCXX_SIMD_HAVE_FMA 0
141 #define _GLIBCXX_SIMD_HAVE_FMA4 1
143 #define _GLIBCXX_SIMD_HAVE_FMA4 0
146 #define _GLIBCXX_SIMD_HAVE_F16C 1
148 #define _GLIBCXX_SIMD_HAVE_F16C 0
151 #define _GLIBCXX_SIMD_HAVE_POPCNT 1
153 #define _GLIBCXX_SIMD_HAVE_POPCNT 0
156 #define _GLIBCXX_SIMD_HAVE_AVX512F 1
158 #define _GLIBCXX_SIMD_HAVE_AVX512F 0
161 #define _GLIBCXX_SIMD_HAVE_AVX512DQ 1
163 #define _GLIBCXX_SIMD_HAVE_AVX512DQ 0
166 #define _GLIBCXX_SIMD_HAVE_AVX512VL 1
168 #define _GLIBCXX_SIMD_HAVE_AVX512VL 0
171 #define _GLIBCXX_SIMD_HAVE_AVX512BW 1
173 #define _GLIBCXX_SIMD_HAVE_AVX512BW 0
176 #if _GLIBCXX_SIMD_HAVE_SSE
177 #define _GLIBCXX_SIMD_HAVE_SSE_ABI 1
179 #define _GLIBCXX_SIMD_HAVE_SSE_ABI 0
181 #if _GLIBCXX_SIMD_HAVE_SSE2
182 #define _GLIBCXX_SIMD_HAVE_FULL_SSE_ABI 1
184 #define _GLIBCXX_SIMD_HAVE_FULL_SSE_ABI 0
187 #if _GLIBCXX_SIMD_HAVE_AVX
188 #define _GLIBCXX_SIMD_HAVE_AVX_ABI 1
190 #define _GLIBCXX_SIMD_HAVE_AVX_ABI 0
192 #if _GLIBCXX_SIMD_HAVE_AVX2
193 #define _GLIBCXX_SIMD_HAVE_FULL_AVX_ABI 1
195 #define _GLIBCXX_SIMD_HAVE_FULL_AVX_ABI 0
198 #if _GLIBCXX_SIMD_HAVE_AVX512F
199 #define _GLIBCXX_SIMD_HAVE_AVX512_ABI 1
201 #define _GLIBCXX_SIMD_HAVE_AVX512_ABI 0
203 #if _GLIBCXX_SIMD_HAVE_AVX512BW
204 #define _GLIBCXX_SIMD_HAVE_FULL_AVX512_ABI 1
206 #define _GLIBCXX_SIMD_HAVE_FULL_AVX512_ABI 0
209 #if defined __x86_64__ && !_GLIBCXX_SIMD_HAVE_SSE2
210 #error "Use of SSE2 is required on AMD64"
215 #define _GLIBCXX_SIMD_NORMAL_MATH
217 #define _GLIBCXX_SIMD_NORMAL_MATH \
218 [[__gnu__::__optimize__("finite-math-only,no-signed-zeros")]]
220 #define _GLIBCXX_SIMD_NEVER_INLINE [[__gnu__::__noinline__]]
221 #define _GLIBCXX_SIMD_INTRINSIC \
222 [[__gnu__::__always_inline__, __gnu__::__artificial__]] inline
223 #define _GLIBCXX_SIMD_ALWAYS_INLINE [[__gnu__::__always_inline__]] inline
224 #define _GLIBCXX_SIMD_IS_UNLIKELY(__x) __builtin_expect(__x, 0)
225 #define _GLIBCXX_SIMD_IS_LIKELY(__x) __builtin_expect(__x, 1)
227 #if defined __STRICT_ANSI__ && __STRICT_ANSI__
228 #define _GLIBCXX_SIMD_CONSTEXPR
229 #define _GLIBCXX_SIMD_USE_CONSTEXPR_API const
231 #define _GLIBCXX_SIMD_CONSTEXPR constexpr
232 #define _GLIBCXX_SIMD_USE_CONSTEXPR_API constexpr
235 #if defined __clang__
236 #define _GLIBCXX_SIMD_USE_CONSTEXPR const
238 #define _GLIBCXX_SIMD_USE_CONSTEXPR constexpr
241 #define _GLIBCXX_SIMD_LIST_BINARY(__macro) __macro(|) __macro(&) __macro(^)
242 #define _GLIBCXX_SIMD_LIST_SHIFTS(__macro) __macro(<<) __macro(>>)
243 #define _GLIBCXX_SIMD_LIST_ARITHMETICS(__macro) \
244 __macro(+) __macro(-) __macro(*) __macro(/) __macro(%)
246 #define _GLIBCXX_SIMD_ALL_BINARY(__macro) \
247 _GLIBCXX_SIMD_LIST_BINARY(__macro) static_assert(true)
248 #define _GLIBCXX_SIMD_ALL_SHIFTS(__macro) \
249 _GLIBCXX_SIMD_LIST_SHIFTS(__macro) static_assert(true)
250 #define _GLIBCXX_SIMD_ALL_ARITHMETICS(__macro) \
251 _GLIBCXX_SIMD_LIST_ARITHMETICS(__macro) static_assert(true)
253 #ifdef _GLIBCXX_SIMD_NO_ALWAYS_INLINE
254 #undef _GLIBCXX_SIMD_ALWAYS_INLINE
255 #define _GLIBCXX_SIMD_ALWAYS_INLINE inline
256 #undef _GLIBCXX_SIMD_INTRINSIC
257 #define _GLIBCXX_SIMD_INTRINSIC inline
260 #if _GLIBCXX_SIMD_HAVE_SSE || _GLIBCXX_SIMD_HAVE_MMX
261 #define _GLIBCXX_SIMD_X86INTRIN 1
263 #define _GLIBCXX_SIMD_X86INTRIN 0
270 #define _GLIBCXX_SIMD_USE_ALIASING_LOADS 1
273 #if _GLIBCXX_SIMD_X86INTRIN
274 #define _GLIBCXX_SIMD_WORKAROUND_PR85048 1
278 #define _GLIBCXX_SIMD_WORKAROUND_PR90993 1
282 #if _GLIBCXX_SIMD_X86INTRIN
283 #define _GLIBCXX_SIMD_WORKAROUND_XXX_1 1
287 #define _GLIBCXX_SIMD_WORKAROUND_PR90424 1
290 #if _GLIBCXX_SIMD_X86INTRIN
291 #define _GLIBCXX_SIMD_WORKAROUND_XXX_3 1
296 #define _GLIBCXX_SIMD_FIX_P2TS_ISSUE65 1
300 #define _GLIBCXX_SIMD_FIX_P2TS_ISSUE66 1