op_names.c
00001 /*
00002  * $Id: op_names.c,v 1.5 2003/12/01 09:10:15 troth Exp $
00003  *
00004  ****************************************************************************
00005  *
00006  * simulavr - A simulator for the Atmel AVR family of microcontrollers.
00007  * Copyright (C) 2001, 2002, 2003  Theodore A. Roth
00008  *
00009  * This program is free software; you can redistribute it and/or modify
00010  * it under the terms of the GNU General Public License as published by
00011  * the Free Software Foundation; either version 2 of the License, or
00012  * (at your option) any later version.
00013  *
00014  * This program is distributed in the hope that it will be useful,
00015  * but WITHOUT ANY WARRANTY; without even the implied warranty of
00016  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00017  * GNU General Public License for more details.
00018  *
00019  * You should have received a copy of the GNU General Public License
00020  * along with this program; if not, write to the Free Software
00021  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
00022  *
00023  ****************************************************************************
00024  */
00025 
00026 #include "op_names.h"
00027 
00028 /*
00029  * Define a global array of opcode Name strings.
00030  */
00031 
00032 /* *INDENT-OFF */
00033 char *global_opcode_name[NUM_OPCODE_HANLDERS] = {
00034     /* opcodes with no operands */
00035     "BREAK",                    /* 0x9598 - 1001 0101 1001 1000 | BREAK */
00036     "EICALL",                   /* 0x9519 - 1001 0101 0001 1001 | EICALL */
00037     "EIJMP",                    /* 0x9419 - 1001 0100 0001 1001 | EIJMP */
00038     "ELPM",                     /* 0x95D8 - 1001 0101 1101 1000 | ELPM */
00039     "ESPM",                     /* 0x95F8 - 1001 0101 1111 1000 | ESPM */
00040     "ICALL",                    /* 0x9509 - 1001 0101 0000 1001 | ICALL */
00041     "IJMP",                     /* 0x9409 - 1001 0100 0000 1001 | IJMP */
00042     "LPM",                      /* 0x95C8 - 1001 0101 1100 1000 | LPM */
00043     "NOP",                      /* 0x0000 - 0000 0000 0000 0000 | NOP */
00044     "RET",                      /* 0x9508 - 1001 0101 0000 1000 | RET */
00045     "RETI",                     /* 0x9518 - 1001 0101 0001 1000 | RETI */
00046     "SLEEP",                    /* 0x9588 - 1001 0101 1000 1000 | SLEEP */
00047     "SPM",                      /* 0x95E8 - 1001 0101 1110 1000 | SPM */
00048     "WDR",                      /* 0x95A8 - 1001 0101 1010 1000 | WDR */
00049 
00050     /* opcode with a single register (Rd) as operand */
00051     "ASR",                      /* 0x9405 - 1001 010d dddd 0101 | ASR */
00052     "COM",                      /* 0x9400 - 1001 010d dddd 0000 | COM */
00053     "DEC",                      /* 0x940A - 1001 010d dddd 1010 | DEC */
00054     "ELPM_Z",                   /* 0x9006 - 1001 000d dddd 0110 | ELPM */
00055     "ELPM_Z_incr",              /* 0x9007 - 1001 000d dddd 0111 | ELPM */
00056     "INC",                      /* 0x9403 - 1001 010d dddd 0011 | INC */
00057     "LDS",                      /* 0x9000 - 1001 000d dddd 0000 | LDS */
00058     "LD_X",                     /* 0x900C - 1001 000d dddd 1100 | LD */
00059     "LD_X_decr",                /* 0x900E - 1001 000d dddd 1110 | LD */
00060     "LD_X_incr",                /* 0x900D - 1001 000d dddd 1101 | LD */
00061     "LD_Y_decr",                /* 0x900A - 1001 000d dddd 1010 | LD */
00062     "LD_Y_incr",                /* 0x9009 - 1001 000d dddd 1001 | LD */
00063     "LD_Z_decr",                /* 0x9002 - 1001 000d dddd 0010 | LD */
00064     "LD_Z_incr",                /* 0x9001 - 1001 000d dddd 0001 | LD */
00065     "LPM_Z",                    /* 0x9004 - 1001 000d dddd 0100 | LPM */
00066     "LPM_Z_incr",               /* 0x9005 - 1001 000d dddd 0101 | LPM */
00067     "LSR",                      /* 0x9406 - 1001 010d dddd 0110 | LSR */
00068     "NEG",                      /* 0x9401 - 1001 010d dddd 0001 | NEG */
00069     "POP",                      /* 0x900F - 1001 000d dddd 1111 | POP */
00070     "PUSH",                     /* 0x920F - 1001 001d dddd 1111 | PUSH */
00071     "ROR",                      /* 0x9407 - 1001 010d dddd 0111 | ROR */
00072     "STS",                      /* 0x9200 - 1001 001d dddd 0000 | STS */
00073     "ST_X",                     /* 0x920C - 1001 001d dddd 1100 | ST */
00074     "ST_X_decr",                /* 0x920E - 1001 001d dddd 1110 | ST */
00075     "ST_X_incr",                /* 0x920D - 1001 001d dddd 1101 | ST */
00076     "ST_Y_decr",                /* 0x920A - 1001 001d dddd 1010 | ST */
00077     "ST_Y_incr",                /* 0x9209 - 1001 001d dddd 1001 | ST */
00078     "ST_Z_decr",                /* 0x9202 - 1001 001d dddd 0010 | ST */
00079     "ST_Z_incr",                /* 0x9201 - 1001 001d dddd 0001 | ST */
00080     "SWAP",                     /* 0x9402 - 1001 010d dddd 0010 | SWAP */
00081 
00082     /* opcodes with two 5-bit register (Rd and Rr) operands */
00083     "ADC",                      /* 0x1C00 - 0001 11rd dddd rrrr | ADC or ROL */
00084     "ADD",                      /* 0x0C00 - 0000 11rd dddd rrrr | ADD or LSL */
00085     "AND",                      /* 0x2000 - 0010 00rd dddd rrrr | AND or TST
00086                                    or LSL */
00087     "CP",                       /* 0x1400 - 0001 01rd dddd rrrr | CP */
00088     "CPC",                      /* 0x0400 - 0000 01rd dddd rrrr | CPC */
00089     "CPSE",                     /* 0x1000 - 0001 00rd dddd rrrr | CPSE */
00090     "EOR",                      /* 0x2400 - 0010 01rd dddd rrrr | EOR or CLR */
00091     "MOV",                      /* 0x2C00 - 0010 11rd dddd rrrr | MOV */
00092     "MUL",                      /* 0x9C00 - 1001 11rd dddd rrrr | MUL */
00093     "OR",                       /* 0x2800 - 0010 10rd dddd rrrr | OR */
00094     "SBC",                      /* 0x0800 - 0000 10rd dddd rrrr | SBC */
00095     "SUB",                      /* 0x1800 - 0001 10rd dddd rrrr | SUB */
00096 
00097     /* opcodes with two 4-bit register (Rd and Rr) operands */
00098     "MOVW",                     /* 0x0100 - 0000 0001 dddd rrrr | MOVW */
00099     "MULS",                     /* 0x0200 - 0000 0010 dddd rrrr | MULS */
00100     "MULSU",                    /* 0x0300 - 0000 0011 dddd rrrr | MULSU */
00101 
00102     /* opcodes with two 3-bit register (Rd and Rr) operands */
00103     "FMUL",                     /* 0x0308 - 0000 0011 0ddd 1rrr | FMUL */
00104     "FMULS",                    /* 0x0380 - 0000 0011 1ddd 0rrr | FMULS */
00105     "FMULSU",                   /* 0x0388 - 0000 0011 1ddd 1rrr | FMULSU */
00106 
00107     /* opcodes with a register (Rd) and a constant data (K) as operands */
00108     "ANDI",                     /* 0x7000 - 0111 KKKK dddd KKKK | CBR or
00109                                    ANDI */
00110     "CPI",                      /* 0x3000 - 0011 KKKK dddd KKKK | CPI */
00111     "LDI",                      /* 0xE000 - 1110 KKKK dddd KKKK | LDI */
00112     "ORI",                      /* 0x6000 - 0110 KKKK dddd KKKK | SBR or ORI */
00113     "SBCI",                     /* 0x4000 - 0100 KKKK dddd KKKK | SBCI */
00114     "SUBI",                     /* 0x5000 - 0101 KKKK dddd KKKK | SUBI */
00115 
00116     /* opcodes with a register (Rd) and a register bit number (b) as
00117        operands */
00118     "BLD",                      /* 0xF800 - 1111 100d dddd 0bbb | BLD */
00119     "BST",                      /* 0xFA00 - 1111 101d dddd 0bbb | BST */
00120     "SBRC",                     /* 0xFC00 - 1111 110d dddd 0bbb | SBRC */
00121     "SBRS",                     /* 0xFE00 - 1111 111d dddd 0bbb | SBRS */
00122 
00123     /* opcodes with a relative 7-bit address (k) and a register bit number (b)
00124        as operands */
00125     "BRBC",                     /* 0xF400 - 1111 01kk kkkk kbbb | BRBC */
00126     "BRBS",                     /* 0xF000 - 1111 00kk kkkk kbbb | BRBS */
00127 
00128     /* opcodes with a 6-bit address displacement (q) and a register (Rd) as
00129        operands */
00130     "LDD_Y",                    /* 0x8008 - 10q0 qq0d dddd 1qqq | LDD */
00131     "LDD_Z",                    /* 0x8000 - 10q0 qq0d dddd 0qqq | LDD */
00132     "STD_Y",                    /* 0x8208 - 10q0 qq1d dddd 1qqq | STD */
00133     "STD_Z",                    /* 0x8200 - 10q0 qq1d dddd 0qqq | STD */
00134 
00135     /* opcodes with a absolute 22-bit address (k) operand */
00136     "CALL",                     /* 0x940E - 1001 010k kkkk 111k | CALL */
00137     "JMP",                      /* 0x940C - 1001 010k kkkk 110k | JMP */
00138 
00139     /* opcode with a sreg bit select (s) operand */
00140     "BCLR",                     /* 0x9488 - 1001 0100 1sss 1000 | BCLR or
00141                                    CL{C,Z,N,V,S,H,T,I} */
00142     "BSET",                     /* 0x9408 - 1001 0100 0sss 1000 | BSET or
00143                                    SE{C,Z,N,V,S,H,T,I} */
00144 
00145     /* opcodes with a 6-bit constant (K) and a register (Rd) as operands */
00146     "ADIW",                     /* 0x9600 - 1001 0110 KKdd KKKK | ADIW */
00147     "SBIW",                     /* 0x9700 - 1001 0111 KKdd KKKK | SBIW */
00148 
00149     /* opcodes with a 5-bit IO Addr (A) and register bit number (b) as
00150        operands */
00151     "CBI",                      /* 0x9800 - 1001 1000 AAAA Abbb | CBI */
00152     "SBI",                      /* 0x9A00 - 1001 1010 AAAA Abbb | SBI */
00153     "SBIC",                     /* 0x9900 - 1001 1001 AAAA Abbb | SBIC */
00154     "SBIS",                     /* 0x9B00 - 1001 1011 AAAA Abbb | SBIS */
00155 
00156     /* opcodes with a 6-bit IO Addr (A) and register (Rd) as operands */
00157     "IN",                       /* 0xB000 - 1011 0AAd dddd AAAA | IN */
00158     "OUT",                      /* 0xB800 - 1011 1AAd dddd AAAA | OUT */
00159 
00160     /* opcodes with a relative 12-bit address (k) operand */
00161     "RCALL",                    /* 0xD000 - 1101 kkkk kkkk kkkk | RCALL */
00162     "RJMP"                      /* 0xC000 - 1100 kkkk kkkk kkkk | RJMP */
00163 };
00164 
00165 /* *INDENT-ON */