Intel(R) Threading Building Blocks Doxygen Documentation  version 4.2.3
sunos_sparc.h
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1 /*
2  Copyright (c) 2005-2019 Intel Corporation
3 
4  Licensed under the Apache License, Version 2.0 (the "License");
5  you may not use this file except in compliance with the License.
6  You may obtain a copy of the License at
7 
8  http://www.apache.org/licenses/LICENSE-2.0
9 
10  Unless required by applicable law or agreed to in writing, software
11  distributed under the License is distributed on an "AS IS" BASIS,
12  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13  See the License for the specific language governing permissions and
14  limitations under the License.
15 
16 
17 
18 
19 */
20 
21 
22 #if !defined(__TBB_machine_H) || defined(__TBB_machine_sunos_sparc_H)
23 #error Do not #include this internal file directly; use public TBB headers instead.
24 #endif
25 
26 #define __TBB_machine_sunos_sparc_H
27 
28 #include <stdint.h>
29 #include <unistd.h>
30 
31 #define __TBB_WORDSIZE 8
32 // Big endian is assumed for SPARC.
33 // While hardware may support page-specific bi-endianness, only big endian pages may be exposed to TBB
34 #define __TBB_ENDIANNESS __TBB_ENDIAN_BIG
35 
38 #define __TBB_compiler_fence() __asm__ __volatile__ ("": : :"memory")
39 #define __TBB_control_consistency_helper() __TBB_compiler_fence()
40 #define __TBB_acquire_consistency_helper() __TBB_compiler_fence()
41 #define __TBB_release_consistency_helper() __TBB_compiler_fence()
42 #define __TBB_full_memory_fence() __asm__ __volatile__("membar #LoadLoad|#LoadStore|#StoreStore|#StoreLoad": : : "memory")
43 
44 //--------------------------------------------------
45 // Compare and swap
46 //--------------------------------------------------
47 
55 static inline int32_t __TBB_machine_cmpswp4(volatile void *ptr, int32_t value, int32_t comparand ){
56  int32_t result;
57  __asm__ __volatile__(
58  "cas\t[%5],%4,%1"
59  : "=m"(*(int32_t *)ptr), "=r"(result)
60  : "m"(*(int32_t *)ptr), "1"(value), "r"(comparand), "r"(ptr)
61  : "memory");
62  return result;
63 }
64 
72 static inline int64_t __TBB_machine_cmpswp8(volatile void *ptr, int64_t value, int64_t comparand ){
73  int64_t result;
74  __asm__ __volatile__(
75  "casx\t[%5],%4,%1"
76  : "=m"(*(int64_t *)ptr), "=r"(result)
77  : "m"(*(int64_t *)ptr), "1"(value), "r"(comparand), "r"(ptr)
78  : "memory");
79  return result;
80 }
81 
82 //---------------------------------------------------
83 // Fetch and add
84 //---------------------------------------------------
85 
92 static inline int32_t __TBB_machine_fetchadd4(volatile void *ptr, int32_t addend){
93  int32_t result;
94  __asm__ __volatile__ (
95  "0:\t add\t %3, %4, %0\n" // do addition
96  "\t cas\t [%2], %3, %0\n" // cas to store result in memory
97  "\t cmp\t %3, %0\n" // check if value from memory is original
98  "\t bne,a,pn\t %%icc, 0b\n" // if not try again
99  "\t mov %0, %3\n" // use branch delay slot to move new value in memory to be added
100  : "=&r"(result), "=m"(*(int32_t *)ptr)
101  : "r"(ptr), "r"(*(int32_t *)ptr), "r"(addend), "m"(*(int32_t *)ptr)
102  : "ccr", "memory");
103  return result;
104 }
105 
112 static inline int64_t __TBB_machine_fetchadd8(volatile void *ptr, int64_t addend){
113  int64_t result;
114  __asm__ __volatile__ (
115  "0:\t add\t %3, %4, %0\n" // do addition
116  "\t casx\t [%2], %3, %0\n" // cas to store result in memory
117  "\t cmp\t %3, %0\n" // check if value from memory is original
118  "\t bne,a,pn\t %%xcc, 0b\n" // if not try again
119  "\t mov %0, %3\n" // use branch delay slot to move new value in memory to be added
120  : "=&r"(result), "=m"(*(int64_t *)ptr)
121  : "r"(ptr), "r"(*(int64_t *)ptr), "r"(addend), "m"(*(int64_t *)ptr)
122  : "ccr", "memory");
123  return result;
124 }
125 
126 //--------------------------------------------------------
127 // Logarithm (base two, integer)
128 //--------------------------------------------------------
129 
130 static inline int64_t __TBB_machine_lg( uint64_t x ) {
131  __TBB_ASSERT(x, "__TBB_Log2(0) undefined");
132  uint64_t count;
133  // one hot encode
134  x |= (x >> 1);
135  x |= (x >> 2);
136  x |= (x >> 4);
137  x |= (x >> 8);
138  x |= (x >> 16);
139  x |= (x >> 32);
140  // count 1's
141  __asm__ ("popc %1, %0" : "=r"(count) : "r"(x) );
142  return count-1;
143 }
144 
145 //--------------------------------------------------------
146 
147 static inline void __TBB_machine_or( volatile void *ptr, uint64_t value ) {
148  __asm__ __volatile__ (
149  "0:\t or\t %2, %3, %%g1\n" // do operation
150  "\t casx\t [%1], %2, %%g1\n" // cas to store result in memory
151  "\t cmp\t %2, %%g1\n" // check if value from memory is original
152  "\t bne,a,pn\t %%xcc, 0b\n" // if not try again
153  "\t mov %%g1, %2\n" // use branch delay slot to move new value in memory to be added
154  : "=m"(*(int64_t *)ptr)
155  : "r"(ptr), "r"(*(int64_t *)ptr), "r"(value), "m"(*(int64_t *)ptr)
156  : "ccr", "g1", "memory");
157 }
158 
159 static inline void __TBB_machine_and( volatile void *ptr, uint64_t value ) {
160  __asm__ __volatile__ (
161  "0:\t and\t %2, %3, %%g1\n" // do operation
162  "\t casx\t [%1], %2, %%g1\n" // cas to store result in memory
163  "\t cmp\t %2, %%g1\n" // check if value from memory is original
164  "\t bne,a,pn\t %%xcc, 0b\n" // if not try again
165  "\t mov %%g1, %2\n" // use branch delay slot to move new value in memory to be added
166  : "=m"(*(int64_t *)ptr)
167  : "r"(ptr), "r"(*(int64_t *)ptr), "r"(value), "m"(*(int64_t *)ptr)
168  : "ccr", "g1", "memory");
169 }
170 
171 
172 static inline void __TBB_machine_pause( int32_t delay ) {
173  // do nothing, inlined, doesn't matter
174 }
175 
176 // put 0xff in memory location, return memory value,
177 // generic trylockbyte puts 0x01, however this is fine
178 // because all that matters is that 0 is unlocked
179 static inline bool __TBB_machine_trylockbyte(unsigned char &flag){
180  unsigned char result;
181  __asm__ __volatile__ (
182  "ldstub\t [%2], %0\n"
183  : "=r"(result), "=m"(flag)
184  : "r"(&flag), "m"(flag)
185  : "memory");
186  return result == 0;
187 }
188 
189 #define __TBB_USE_GENERIC_PART_WORD_CAS 1
190 #define __TBB_USE_GENERIC_PART_WORD_FETCH_ADD 1
191 #define __TBB_USE_GENERIC_FETCH_STORE 1
192 #define __TBB_USE_GENERIC_HALF_FENCED_LOAD_STORE 1
193 #define __TBB_USE_GENERIC_RELAXED_LOAD_STORE 1
194 #define __TBB_USE_GENERIC_SEQUENTIAL_CONSISTENCY_LOAD_STORE 1
195 
196 #define __TBB_AtomicOR(P,V) __TBB_machine_or(P,V)
197 #define __TBB_AtomicAND(P,V) __TBB_machine_and(P,V)
198 
199 // Definition of other functions
200 #define __TBB_Pause(V) __TBB_machine_pause(V)
201 #define __TBB_Log2(V) __TBB_machine_lg(V)
202 
203 #define __TBB_TryLockByte(P) __TBB_machine_trylockbyte(P)
static int64_t __TBB_machine_lg(uint64_t x)
Definition: sunos_sparc.h:130
#define __TBB_ASSERT(predicate, comment)
No-op version of __TBB_ASSERT.
Definition: tbb_stddef.h:169
static int32_t __TBB_machine_fetchadd4(volatile void *ptr, int32_t addend)
Definition: sunos_sparc.h:92
void const char const char int ITT_FORMAT __itt_group_sync x void const char ITT_FORMAT __itt_group_sync s void ITT_FORMAT __itt_group_sync p void ITT_FORMAT p void ITT_FORMAT p no args __itt_suppress_mode_t unsigned int void size_t ITT_FORMAT d void ITT_FORMAT p void ITT_FORMAT p __itt_model_site __itt_model_site_instance ITT_FORMAT p __itt_model_task __itt_model_task_instance ITT_FORMAT p void ITT_FORMAT p void ITT_FORMAT p void size_t ITT_FORMAT d void ITT_FORMAT p const wchar_t ITT_FORMAT s const char ITT_FORMAT s const char ITT_FORMAT s const char ITT_FORMAT s no args void ITT_FORMAT p size_t count
static int64_t __TBB_machine_fetchadd8(volatile void *ptr, int64_t addend)
Definition: sunos_sparc.h:112
void const char const char int ITT_FORMAT __itt_group_sync x void const char ITT_FORMAT __itt_group_sync s void ITT_FORMAT __itt_group_sync p void ITT_FORMAT p void ITT_FORMAT p no args __itt_suppress_mode_t unsigned int void size_t ITT_FORMAT d void ITT_FORMAT p void ITT_FORMAT p __itt_model_site __itt_model_site_instance ITT_FORMAT p __itt_model_task __itt_model_task_instance ITT_FORMAT p void ITT_FORMAT p void ITT_FORMAT p void size_t ITT_FORMAT d void ITT_FORMAT p const wchar_t ITT_FORMAT s const char ITT_FORMAT s const char ITT_FORMAT s const char ITT_FORMAT s no args void ITT_FORMAT p size_t ITT_FORMAT d no args const wchar_t const wchar_t ITT_FORMAT s __itt_heap_function void size_t int ITT_FORMAT d __itt_heap_function void ITT_FORMAT p __itt_heap_function void void size_t int ITT_FORMAT d no args no args unsigned int ITT_FORMAT u const __itt_domain __itt_id ITT_FORMAT lu const __itt_domain __itt_id __itt_id __itt_string_handle ITT_FORMAT p const __itt_domain __itt_id ITT_FORMAT p const __itt_domain __itt_id __itt_timestamp __itt_timestamp ITT_FORMAT lu const __itt_domain __itt_id __itt_id __itt_string_handle ITT_FORMAT p const __itt_domain ITT_FORMAT p const __itt_domain __itt_string_handle unsigned long long value
static void __TBB_machine_or(volatile void *ptr, uint64_t value)
Definition: sunos_sparc.h:147
static bool __TBB_machine_trylockbyte(unsigned char &flag)
Definition: sunos_sparc.h:179
static int64_t __TBB_machine_cmpswp8(volatile void *ptr, int64_t value, int64_t comparand)
Definition: sunos_sparc.h:72
static int32_t __TBB_machine_cmpswp4(volatile void *ptr, int32_t value, int32_t comparand)
Definition: sunos_sparc.h:55
static void __TBB_machine_pause(int32_t delay)
Definition: sunos_sparc.h:172
static void __TBB_machine_and(volatile void *ptr, uint64_t value)
Definition: sunos_sparc.h:159

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