25 #ifndef __TBB_machine_H 26 #error Do not include this file directly; include tbb_machine.h instead 31 #include <sys/param.h> 34 #define __TBB_WORDSIZE 4 41 #if __BIG_ENDIAN__ || (defined(__BYTE_ORDER__) && __BYTE_ORDER__==__ORDER_BIG_ENDIAN__) 42 #define __TBB_ENDIANNESS __TBB_ENDIAN_BIG 43 #elif __LITTLE_ENDIAN__ || (defined(__BYTE_ORDER__) && __BYTE_ORDER__==__ORDER_LITTLE_ENDIAN__) 44 #define __TBB_ENDIANNESS __TBB_ENDIAN_LITTLE 45 #elif defined(__BYTE_ORDER__) 46 #define __TBB_ENDIANNESS __TBB_ENDIAN_UNSUPPORTED 48 #define __TBB_ENDIANNESS __TBB_ENDIAN_DETECT 52 #define __TBB_compiler_fence() __asm__ __volatile__("": : :"memory") 53 #define __TBB_full_memory_fence() __asm__ __volatile__("dmb ish": : :"memory") 54 #define __TBB_control_consistency_helper() __TBB_full_memory_fence() 55 #define __TBB_acquire_consistency_helper() __TBB_full_memory_fence() 56 #define __TBB_release_consistency_helper() __TBB_full_memory_fence() 81 "strexeq %0, %5, [%3]\n" 82 :
"=&r" (res),
"=&r" (oldval),
"+Qo" (*(
volatile int32_t*)ptr)
83 :
"r" ((
volatile int32_t *)ptr),
"Ir" (comparand),
"r" (
value)
107 __asm__ __volatile__(
109 "ldrexd %1, %H1, [%3]\n" 114 "strexdeq %0, %5, %H5, [%3]" 115 :
"=&r" (res),
"=&r" (oldval),
"+Qo" (*(
volatile int64_t*)ptr)
116 :
"r" ((
volatile int64_t *)ptr),
"r" (comparand),
"r" (
value)
128 int32_t result, tmp2;
132 __asm__ __volatile__(
133 "1: ldrex %0, [%4]\n" 135 " strex %1, %3, [%4]\n" 138 :
"=&r" (result),
"=&r" (tmp),
"+Qo" (*(
volatile int32_t*)ptr),
"=&r"(tmp2)
139 :
"r" ((
volatile int32_t *)ptr),
"Ir" (addend)
150 int64_t result, tmp2;
154 __asm__ __volatile__(
155 "1: ldrexd %0, %H0, [%4]\n" 157 " adc %H3, %H0, %H5\n" 158 " strexd %1, %3, %H3, [%4]\n" 161 :
"=&r" (result),
"=&r" (tmp),
"+Qo" (*(
volatile int64_t*)ptr),
"=&r"(tmp2)
162 :
"r" ((
volatile int64_t *)ptr),
"r" (addend)
173 template <
typename T,
size_t S>
174 struct machine_load_store_relaxed {
175 static inline T
load (
const volatile T& location ) {
176 const T
value = location;
186 static inline void store (
volatile T& location, T
value ) {
194 #define __TBB_CompareAndSwap4(P,V,C) __TBB_machine_cmpswp4(P,V,C) 195 #define __TBB_CompareAndSwap8(P,V,C) __TBB_machine_cmpswp8(P,V,C) 198 #define __TBB_USE_GENERIC_PART_WORD_CAS 1 199 #define __TBB_USE_GENERIC_PART_WORD_FETCH_ADD 1 200 #define __TBB_USE_GENERIC_PART_WORD_FETCH_STORE 1 201 #define __TBB_USE_GENERIC_FETCH_STORE 1 202 #define __TBB_USE_GENERIC_HALF_FENCED_LOAD_STORE 1 203 #define __TBB_USE_GENERIC_DWORD_LOAD_STORE 1 204 #define __TBB_USE_GENERIC_SEQUENTIAL_CONSISTENCY_LOAD_STORE 1 205 #elif defined __aarch64__ 209 #error compilation requires an ARMv7-a or ARMv8-a architecture. 210 #endif // __ARM_ARCH_7A__ 216 __asm__ __volatile__(
"yield" :::
"memory");
220 #define __TBB_Pause(V) __TBB_machine_pause(V) #define __TBB_acquire_consistency_helper()
#define __TBB_full_memory_fence()
void const char const char int ITT_FORMAT __itt_group_sync x void const char ITT_FORMAT __itt_group_sync s void ITT_FORMAT __itt_group_sync p void ITT_FORMAT p void ITT_FORMAT p no args __itt_suppress_mode_t unsigned int void size_t ITT_FORMAT d void ITT_FORMAT p void ITT_FORMAT p __itt_model_site __itt_model_site_instance ITT_FORMAT p __itt_model_task __itt_model_task_instance ITT_FORMAT p void ITT_FORMAT p void ITT_FORMAT p void size_t ITT_FORMAT d void ITT_FORMAT p const wchar_t ITT_FORMAT s const char ITT_FORMAT s const char ITT_FORMAT s const char ITT_FORMAT s no args void ITT_FORMAT p size_t ITT_FORMAT d no args const wchar_t const wchar_t ITT_FORMAT s __itt_heap_function void size_t int ITT_FORMAT d __itt_heap_function void ITT_FORMAT p __itt_heap_function void void size_t int ITT_FORMAT d no args no args unsigned int ITT_FORMAT u const __itt_domain __itt_id ITT_FORMAT lu const __itt_domain __itt_id __itt_id __itt_string_handle ITT_FORMAT p const __itt_domain __itt_id ITT_FORMAT p const __itt_domain __itt_id __itt_timestamp __itt_timestamp ITT_FORMAT lu const __itt_domain __itt_id __itt_id __itt_string_handle ITT_FORMAT p const __itt_domain ITT_FORMAT p const __itt_domain __itt_string_handle unsigned long long value
long __TBB_machine_fetchadd4(volatile void *ptr, __int32 addend)
static void store(T &location, T value)
#define __TBB_machine_cmpswp8
static int64_t __TBB_machine_fetchadd8(volatile void *ptr, int64_t addend)
#define __TBB_machine_cmpswp4
void __TBB_machine_pause(int32_t delay)
static T load(const T &location)